Selective compilation of a simulation model in view of unavailable higher level signals
US8160857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Oct 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.