Method and system for a RFIC master
US8161217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2011 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Jul 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.