Interface between a twin-wire bus and a single-wire bus
US8161224B2 · kind B2 · utility
55Cited by
3References
9Claims
0Family size
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Key dates
| Filing date | Jul 14, 2009 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Oct 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.