Flash memory controller having configuring unit for error correction code (ECC) capability and method thereof
US8161354B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Feb 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory controller includes a control unit, a buffer, an error correction code (ECC) module, and a configuring unit. The flash memory has a data area for storing the data content and a first spare area for storing a first ECC value corresponding to the data content. The ECC module utilizes the data content for generating a second ECC value and comparing the second ECC value with the first ECC value to determine whether the data content comprises a plurality of errors. The configuring unit computes the amount of the errors to determine whether the amount of the errors exceeds a predetermined threshold. If The configuring unit configures the data area and assigns a portion of the data area to be a second spare area. The first and the second spare area are associated with the ECC capability to allow the ECC module to correct the errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.