Reset mechanism conversion
US8161435B2 · kind B2 · utility
6Cited by
12References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2009 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Jul 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.