Pixel structure and fabricating method thereof
US8164094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2010 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Oct 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1362
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In a fabricating method of a pixel structure, a scan line and a gate electrode are formed in each pixel area of a substrate. A gate insulation layer is formed to cover the scan line and gate electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. A data line, source and drain are formed in each pixel area. A first passivation layer covers the data line, source and drain. A common line is formed on the first passivation layer and overlaps with at least a portion of the data line. A common electrode is formed on and electrically connected with the common line. A second passivation layer covers the common electrode and common line. A contact window is formed in the second passivation layer above the drain to expose the drain. A pixel electrode is electrically connected with the drain through the contact window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.