Data line structure in lead region
US8164194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2008 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Jan 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An embodiment of the invention provides a data line structure in a lead region of a thin film transistor liquid crystal display (TFT-LCD). The data line structure in the lead region comprises a substrate and a gate layer data line segment, a dielectric layer, a data line lead, and a passivation layer, which are formed sequentially in the lead region on the substrate. The gate layer data line segment extends corresponding to the data line lead; the data line lead is formed with a via hole therein; a portion of the gate insulating layer and a portion of the passivation layer in a position corresponding to the via hole are removed so as to form a connection hole together with the via hole; a connection line segment is formed in the connection hole, and the gate layer data line segment and the data line lead are connected by the connection line segment in the connection hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.