Digital noise protection circuit and method
US8164357B2 · kind B2 · utility
4Cited by
3References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 27, 2010 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Apr 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.