Synchronization of multiple high frequency switching power converters in an integrated circuit
US8164391B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2010 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Sep 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0893
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A phase locked loop is used to synchronize the switching frequency of a high frequency switching power converter to a clock signal. A switching power converter integrated circuit is a tile-based power management unit and includes an oscillator and multiple tiles of switching power converters. The oscillator generates a clock signal having a clock frequency. A first switching power converter includes a switch and a phase locked loop and switches at a first frequency. The switch has a gate that receives a gate signal. The phase locked loop synchronizes the first frequency to a first integer multiple of the clock frequency. A second switching power converter switches at a second frequency that is a second integer multiple of the clock frequency. The first frequency is synchronized to a multiple of the clock frequency when a second edge of the gate signal coincides with a first edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.