Pipeline analog-to-digital converter
US8164497B2 · kind B2 · utility
1Cited by
2References
10Claims
0Family size
Assignee
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Key dates
| Filing date | May 11, 2010 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Aug 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.