Semiconductor memory device
US8164938B2 · kind B2 · utility
16Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2010 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Dec 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.