Dual power rail word line driver and dual power rail word line driver array
US8164971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2010 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Nov 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is coupled between the word line and a node. A pull-down unit is coupled between the node and a ground. A pull-up unit is coupled between the node and a second supply voltage higher than or equal to the first supply voltage. The signal buffering unit provides a word line signal corresponding to the predecode signal to the memory array via the word line when the pull-down unit is turned on by the predecode signal and a first pulse signal and the pull-up unit is turned off by a second pulse signal. There is no level shifter on a critical timing path of the dual power rail word line driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.