Method and arrangement for preamble detection
US8165103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2006 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Jan 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W74/08
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a hardware accelerator for preamble detection of a Physical Random Access Channel (PRACH) in a CDMA based communication system, buffering means stores input samples received at an antenna at a first rate, addressing means read a predetermined consecutive number of the input samples in parallel at a second different rate. The hardware accelerator is further partitioned into a reusable unit providing code correlation, and a preamble detection dedicated unit providing signature code despreading. The reusable unit comprises means for correlating at least a subset of the previously read input samples with a predetermined code to provide a correlation output for a number of time lags. The preamble detection dedicated unit comprises means for preamble detection configured for providing Hadamard Transformation of the correlation output to enable preamble detection, and all means are arranged on a single hardware chip to enable high-speed data transmissions between the respective means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.