Buffering architecture for packet injection and extraction in on-chip networks
US8165120B2 · kind B2 · utility
55Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 10, 2008 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Sep 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3072
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: The control data and the actual data to be transferred are stored in separate first and second memory means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.