Multi-protocol channel-aggregated configurable transceiver in an integrated circuit
US8165191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2008 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Nov 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.