Digital circuit arrangements for ambient noise-reduction
US8165312B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2007 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Apr 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10K2210/3217
- WIPO fieldOther consumer goods
- WIPO sectorOther fields
Abstract
The invention provides a digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible, through the use of a low latency signal processing chain consisting of analogue-to-digital conversion, digital processing and digital-to-analogue conversion. The arrangement converts the analogue signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.