Method to control delay between lanes
US8166215B2 · kind B2 · utility
1Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2005 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Jan 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.