Configurable allocation of thread queue resources in an FPGA
US8166237B1 · kind B1 · utility
23Cited by
1References
22Claims
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Key dates
| Filing date | Oct 23, 2009 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Oct 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexers, and pointers that allow static or dynamic bandwidth configuration as function of instruments examining the system traffic using queues. The interface allows many initiators having many logical threads to share and use many physical threads in different queue modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.