Patent · US Active

Data pipeline with large tuning range of clock signals

US8166286B2 · kind B2 · utility

4Cited by
8References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 11, 2008
Grant dateApr 24, 2012
Priority date
Expiry dateMay 24, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K3/356173
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.