Patent · US Active

Reliable exception handling in a computer system

US8166338B2 · kind B2 · utility

1Cited by

3References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Thomas Huth · Eppelheim, DE
Jan Kunigk · Eppelheim, DE
Joerg-Stephan Vogt · Holzgerlingen, DE

Key dates

Filing date	May 25, 2010
Grant date	Apr 24, 2012
Priority date	—
Expiry date	May 25, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/073
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.