System and method for mitigating memory requirements
US8166355B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2006 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Jul 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver is provided, which is adapted to receive MPE-FEC frames and to correct erroneous sections within a received MPE-FEC frame by detecting unreliable sections and storing in an erasure list (“ESL”) table compressed data that includes the base address of each detected erroneous section, together with the respective section's size. The size of the ESL table may be fixed, or it may correlate, or dynamically change according to the actual number of detected erroneous sections. The data stored in the erasure list may then be forwarded to a decoder to correct erroneous sections. The erroneous sections may be detected by using CRC, and the decoder may be a Reed-Solomon decoder. If the application data table of the MPE-FEC is error-free (or full or errors), in which case the erasure structure list is empty (or full of errors), in which case the erasure structure list is empty (or full), this means that no FEC reception and error corrections are required, because there are no sections to correct in the first case and the decoder is incapable of correcting too many sections in the second case. Therefore, the receiving circuitry, or at least the decoder, may be disabled to save battery…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.