Nonvolatile semiconductor memory device and method of manufacturing the same

US8169016B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventor

• Kazuyuki Higashi · Farmington Hills, US

Key dates

• Filing date: Sep 2, 2010
• Grant date: May 1, 2012
• Expiry date: Oct 23, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/40

Abstract

A plurality of conductive layers are stacked in a first region and a second region. A semiconductor layer is surrounded by the conductive layers in the first region, includes a columnar portion extending in a perpendicular direction with respect to a substrate. A charge storage layer is formed between the conductive layers and a side surface of the columnar portion. The conductive layers includes first trenches, second trenches, and third trenches. The first trenches are arranged in the first region so as to have a first pitch in a first direction. The second trenches are arranged in the second region so as to have a second pitch in the first direction. The third trenches are arranged in the second region so as to have a third pitch in the first direction and so as to be sandwiched by the second trenches.