Signal level conversion circuit
US8169250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2010 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal level conversion circuit includes three or more level shift circuits to output internal output signals upon receiving input signals, respectively. Each of the level shift circuits is formed of a common electrical element and an electrical element connected to the common electrical element. A voltage higher than that supplied to the common electrical element is supplied to the electrical element. A buffer circuit having an input tolerant function is provided in each of the common electrical elements. The internal output signals are set at lower level than the input signals by the buffer circuits, and the internal output signal outputted from one of the level shift circuits is further outputted via other level shift circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.