Distributed tessellation topology generator
US8169437B1 · kind B1 · utility
12Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 9, 2008 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Jan 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for dividing three-dimensional patches into tasks for processing receives control points defining a three dimensional patch and determines if a number of vertices of the three dimensional patch is greater than a maximum value. When the number of vertices is not greater than the maximum value, the three dimensional patch is output as a single task. When the number of vertices is greater than the maximum value, the three dimensional patch is divided into multiple tasks that each include a number of vertices that is not greater than the maximum value and the multiple tasks are output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.