Three-phase buck-boost power factor correction circuit and controlling method thereof
US8169804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2009 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Jul 1, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The configurations of a three-phase buck-boost power factor correction (PFC) circuit are provided. The circuit includes a first single-phase buck-boost PFC circuit receiving a first phase voltage and having a first and a second output terminals and a neutral-point for outputting a first and a second output voltages, a second single-phase buck-boost PFC circuit receiving a third phase voltage and coupled to the first and the second output terminals and the neutral-point, a first to a fourth thyristors, each of which has an anode and a cathode. The anodes of the first and the third thyristors and the cathodes of the second and the fourth thyristors receive a second phase voltage, and the cathode of the first thyristor and the anode of the second thyristor are coupled to the first single-phase buck-boost PFC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.