Processor apparatus
US8170205B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2008 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Oct 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.