Atomic compare and swap using dedicated processor
US8171235B2 · kind B2 · utility
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9References
38Claims
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Key dates
| Filing date | Jan 28, 2009 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An atomic compare and swap operation that can be implemented in processor system having first and second processors that have different sized memory transfer capabilities. The first processor notifies the second processor to perform a compare and swap operation on an address in main memory. The address has a size less than or equal to a maximum memory transfer size for the second processor and greater than a maximum memory transfer size for the first processor. The second processor atomically performs the compare and swap operation and notifies the first processor of the success or failure of the compare and swap operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.