Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions
US8171263B2 · kind B2 · utility
1Cited by
110References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | May 1, 2012 |
| Priority date | — |
| Expiry date | Nov 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.