Standard cell architecture and methods with variable design rules
US8173491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2011 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Mar 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.