Thin film transistor array panel and fabrication
US8173493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2010 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Aug 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13629
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.