Patent · US Active

Stacked multi-chip

US8174126B2 · kind B2 · utility

9Cited by

22References

11Claims

0Family size

Assignee

NATIONAL TSING HUA UNIVERSITY · TW

Inventors

Ting-Ting Hwang · Hsinchu, TW
Hsien-Te Chen · Taipei, TW

Key dates

Filing date	Sep 15, 2010
Grant date	May 8, 2012
Priority date	—
Expiry date	Jan 20, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.