Method and apparatus for improving accuracy of signals delay
US8174298B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2011 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Oct 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay module, includes a first delay unit, a second delay unit and an inverter. Each of the first and second delay units includes: a logic gate for gating and a logic gate for delaying. The input port of the logic gate for gating of the first delay unit is electrically connected to the output port of the inverter; the output port of the logic gate for delaying of the first delay unit is electrically connected to the input port of the logic gate for delaying of the second delay unit; the input port of the inverter is electrically connected to the input port of the logic gate for gating of the second delay unit; the input port of the inverter is adapted to input a clock signal to be delayed, and the logic gate for delaying of the second delay unit is adapted to output a delayed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.