Patent · US Active

Phase-error reduction circuitry for an IQ generator

US8174301B2 · kind B2 · utility

1Cited by

8References

18Claims

0Family size

Assignee

FUJITSU SEMICONDUCTOR LIMITED · JP

Inventors

Robert E. Braun · Bar Harbor, US
Bardo Muller · Dreieich, DE

Key dates

Filing date	Nov 12, 2008
Grant date	May 8, 2012
Priority date	—
Expiry date	Feb 6, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/151
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Phase-error-reduction circuitry for an IQ generator, wherein the phase-error-reduction circuitry is arranged to receive I and Q input signals from the IQ generator and to produce I and Q output signals, and wherein the phase-error-reduction circuitry is arranged to sample the I and Q input signals to tend to reduce a phase error between the I and Q output signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.