Method and system for configuration of a phase-locked loop circuit
US8174327B2 · kind B2 · utility
0Cited by
7References
17Claims
0Family size
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Inventor
Key dates
| Filing date | Apr 12, 2007 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Feb 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1974
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Example embodiments are directed toward configuration of a phase lock loop (PLL) circuits for low power operation. In particular embodiments, a fraction related to a desired gain of a PLL circuit is determined. A set of possible frequency-divider values and a set of possible feedback divider values are determined. A PLL configuration is selected from a combination of the sets of frequency divider and feedback divider values that forms a ratio indicated the determined fraction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.