Power efficient FHSS base-band hardware architecture
US8175138B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 15, 2008 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Feb 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/713
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention provides a power efficient FHSS (Frequency Hopping Spreading Spectrum) base-band hardware architecture, and more particularly to a combinational design to reduce the system jitter of a frequency hopping communication system and bring system synchronization to higher level of performance, thereby achieving better immunity to faulty access header recognition, data corruption by sending and tracking the package header of each package more precise, therefore reduces the uncertain window of access header check. With above-mentioned features, this invention has less error packets resend over wireless link, and maintain same system functionality using MCU clocked at relative lower frequency. Hence it becomes possible to reduce the area of the silicon implementation, extend standby time when used in mobile device, and save power consumption system wide. Moreover, the present invention is applicable for use in various types of base-band hardware communication architectures or similar architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.