Clock domain data transfer device and methods thereof
US8176352B2 · kind B2 · utility
6Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2008 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Mar 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.