Method and system for direct access memory testing of an integrated circuit
US8176370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2004 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Jan 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.