Systems and methods for enhanced flaw scan in a data processing device
US8176400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2009 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Nov 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.