Systems and methods for stepped data retry in a storage system
US8176404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2009 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Nov 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2516
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure window register includes: an erasure flag location, an erasure flag length, and a step size. The erasure flag set circuit is operable to assert a first erasure flag beginning at the erasure flag location and having the erasure flag length at a first time. In addition, the erasure flag set circuit is operable to assert a second erasure flag beginning at the erasure flag location plus the step size, and having the erasure flag length at a second time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.