Fast phase locking system for automatically calibrated fractional-N PLL
US8179174B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Dec 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.