NAND flash memory
US8179720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2010 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Nov 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be written and a semiconductor well, and after the write operation and before performing a verification read operation of verifying whether data has been written into the selected memory cell, the control circuit performs a de-trapping operation, in which a first voltage of a same potential as that of the semiconductor well or a same polarity as that of the writing voltage is applied to the control gate of the selected memory cell and in which a second voltage of a same polarity as that of the writing voltage and larger than the first voltage as an absolute value is applied to a control gate of unselected memory cells not to be written.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.