Programmable duty cycle distortion generation circuit
US8179952B2 · kind B2 · utility
19Cited by
29References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2008 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Aug 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31708
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.