Accelerated screen codec
US8180165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Mar 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An accelerated screen codec technique is described that provides a general screen compression framework, which, in one embodiment, is Graphics Processor Unit (GPU) friendly. In one embodiment, in order to compress screen data, blocks in a compound screen image containing both images and text are segmented into text blocks and pictorial blocks using a simple gradient-based procedure. The text and pictorial blocks are then compressed respectively via different compression techniques. Additionally, a GPU acceleration architecture of one embodiment of the accelerated screen codec technique provides a screen codec that maximally exploits a GPU's high parallelism and reduces the download bandwidth from GPU to Computer Processing Unit (CPU).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.