Deterministic finite automata (DFA) graph compression
US8180803B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2007 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc of a current node represents a character match in an expression of a character associated with the current node. Arcs which are not valid may be pruned. Non-valid arcs may include arcs which point back to a designated node(s), or arcs that point to the same next node as the designated node(s) for the same character. Typically, the majority of arcs associated with a node are non-valid. Therefore, pruning the non-valid arcs may greatly reduce graph storage requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.