Hierarchical read-combining local memories
US8180963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2009 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Jul 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a system for hierarchical read-combining memory having a multicore processor operably coupled to a memory controller. The memory controller is configured for receiving a plurality of requests for data from one or more processing cores of the multicore processor, selectively holding a request for data from the plurality of requests for an undetermined or indefinite amount of time, and selectively combining a plurality of requests for the same data into a single read-combined data request. The present disclosure further relates to a method for hierarchical read-combining data requests of a multicore processor and a computer accessible medium having stored thereon computer executable instructions for performing a procedure for hierarchical read-combining data requests of a multicore processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.