Reduction of cache flush time using a dirty line limiter
US8180968B2 · kind B2 · utility
5Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Jul 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.