Controlling interference in shared memory systems using parallelism-aware batch scheduling
US8180975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2008 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Mar 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism. Further, rank-based request scheduling may be performed with or without batching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.