Integrated circuit including a plurality of master circuits transmitting access requests to an external device and integrated circuit system including first and second interated circuits each including a plurality of master circuits transmitting access requests
US8180990B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Sep 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A main LSI includes a plurality of master circuits transmitting access requests to a SDRAM, and includes an input interface receiving an access request from a master circuit in a sub LSI. Further, the main LSI includes an arbitration circuit receiving the access requests from the internal master circuits and from the input interface, sequentially selecting, in accordance with a predetermined arbitration rule, a master circuit to be allowed to access the SDRAM, and determining output timings for addresses pertaining to the data transfers from the sequentially selected master circuits. The main LSI also includes an access signal generation circuit causing the sequentially selected master circuits to access the SDRAM in accordance with the corresponding output timings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.