Clock-data-recovery technique for high-speed links
US8181058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2010 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Nov 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.