Information processing apparatus for inhibiting instructions, saving and restoring internal information in response to abnormality in redundant processor system
US8181064B2 · kind B2 · utility
4Cited by
13References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 24, 2010 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Mar 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.